Processor overview
The current HarvOS processor is a 32-bit, RISC-V-like bare-metal core with Harvard separation, MMU/MPU checks, supervisor CSRs, two SoC harts, USB/HPS block I/O, HNET network MMIO and a boot-ROM path for loading ELF applications.
CPU architecture diagram
Quick profile
| Property | Current state |
|---|---|
| Register width | HARVOS_XLEN = 32; 32 integer registers with RISC-V-style numbering; x0 is hardwired to zero. |
| ISA base | RV32I-like instruction subset plus three Custom-0 operations: CLRREG, CLRMEM and ENTROPY. |
| RISC-V boundary | Not a complete RISC-V platform: no M, A or C extensions, no PMP CSRs, local CSR layout and HarvOS-specific MMU/MPU rules. |
| Pipeline model | Multi-cycle state machine: FETCH, DECODE, EXEC, MEM, WB and CLRMEM. |
| Harts | Two harvos_cpu instances in harvos_soc, connected through harvos_smp_bus2. |
| Reset | Hart 0 starts at 0x00000000; hart 1 starts at 0x000000c0 in the SoC integration. |
| Trap vector | SoC integration uses 0x000000a0; the CPU default is 0x00000080. |
| Memory model | Harvard: separate fetch path into IMEM and separate data path into DMEM/MMIO. |
| Privileges | Internal PRIV_U, PRIV_S and PRIV_M encodings; boot and current applications run in supervisor contexts. |
| MMU/MPU | Fetch MMU with 32 TLB entries, data MMU with 64 TLB entries, fixed HarvOS MPU checks for IMEM/DMEM/MMIO and Harvard violations. |
| DMA | DMEM bounce window constrained by harvos_dma_iommu. |
Scope and assumptions
This documentation describes the RTL and software present in the project. Some modules are production-shaped hooks or observable models rather than final platform blocks. Cache metadata, coherence counters, secure boot hooks and the kernel model are intentionally visible for testing.
Important assumption: board clocks, reset sequencing,
physical USB PHY, raw Ethernet MAC/PHY integration and external DDR are
platform-dependent. The pages therefore distinguish implemented HarvOS
SoC behavior from integration work required for a concrete board.